| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129 |
- /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- */
-
- #include "cpuport.h"
- .section .text.entry
- .align 6 /* In ECLIC mode, the trap entry must be 64bytes aligned */
- .global irq_entry
- irq_entry:
- /* save all from thread context */
- addi sp, sp, -32 * REGBYTES
- STORE x1, 1 * REGBYTES(sp)
- li t0, 0x80
- STORE t0, 2 * REGBYTES(sp)
- STORE x4, 4 * REGBYTES(sp)
- STORE x5, 5 * REGBYTES(sp)
- STORE x6, 6 * REGBYTES(sp)
- STORE x7, 7 * REGBYTES(sp)
- STORE x8, 8 * REGBYTES(sp)
- STORE x9, 9 * REGBYTES(sp)
- STORE x10, 10 * REGBYTES(sp)
- STORE x11, 11 * REGBYTES(sp)
- STORE x12, 12 * REGBYTES(sp)
- STORE x13, 13 * REGBYTES(sp)
- STORE x14, 14 * REGBYTES(sp)
- STORE x15, 15 * REGBYTES(sp)
- STORE x16, 16 * REGBYTES(sp)
- STORE x17, 17 * REGBYTES(sp)
- STORE x18, 18 * REGBYTES(sp)
- STORE x19, 19 * REGBYTES(sp)
- STORE x20, 20 * REGBYTES(sp)
- STORE x21, 21 * REGBYTES(sp)
- STORE x22, 22 * REGBYTES(sp)
- STORE x23, 23 * REGBYTES(sp)
- STORE x24, 24 * REGBYTES(sp)
- STORE x25, 25 * REGBYTES(sp)
- STORE x26, 26 * REGBYTES(sp)
- STORE x27, 27 * REGBYTES(sp)
- STORE x28, 28 * REGBYTES(sp)
- STORE x29, 29 * REGBYTES(sp)
- STORE x30, 30 * REGBYTES(sp)
- STORE x31, 31 * REGBYTES(sp)
- move s0, sp
- /* switch to interrupt stack */
- la sp, _sp
- /* interrupt handle */
- call rt_interrupt_enter
- csrr a0, mcause
- csrr a1, mepc
- mv a2, sp
- csrrw ra, 0x07ED, ra
- call rt_interrupt_leave
- /* switch to from thread stack */
- move sp, s0
- /* need to switch new thread */
- la s0, rt_thread_switch_interrupt_flag
- lw s2, 0(s0)
- beqz s2, spurious_interrupt
- /* clear switch interrupt flag */
- sw zero, 0(s0)
- csrr a0, mepc
- STORE a0, 0 * REGBYTES(sp)
- la s0, rt_interrupt_from_thread
- LOAD s1, 0(s0)
- STORE sp, 0(s1)
- la s0, rt_interrupt_to_thread
- LOAD s1, 0(s0)
- LOAD sp, 0(s1)
- LOAD a0, 0 * REGBYTES(sp)
- csrw mepc, a0
- spurious_interrupt:
- LOAD x1, 1 * REGBYTES(sp)
- /* Remain in M-mode after mret */
- li t0, 0x00001800
- csrs mstatus, t0
- LOAD t0, 2 * REGBYTES(sp)
- csrs mstatus, t0
- LOAD x4, 4 * REGBYTES(sp)
- LOAD x5, 5 * REGBYTES(sp)
- LOAD x6, 6 * REGBYTES(sp)
- LOAD x7, 7 * REGBYTES(sp)
- LOAD x8, 8 * REGBYTES(sp)
- LOAD x9, 9 * REGBYTES(sp)
- LOAD x10, 10 * REGBYTES(sp)
- LOAD x11, 11 * REGBYTES(sp)
- LOAD x12, 12 * REGBYTES(sp)
- LOAD x13, 13 * REGBYTES(sp)
- LOAD x14, 14 * REGBYTES(sp)
- LOAD x15, 15 * REGBYTES(sp)
- LOAD x16, 16 * REGBYTES(sp)
- LOAD x17, 17 * REGBYTES(sp)
- LOAD x18, 18 * REGBYTES(sp)
- LOAD x19, 19 * REGBYTES(sp)
- LOAD x20, 20 * REGBYTES(sp)
- LOAD x21, 21 * REGBYTES(sp)
- LOAD x22, 22 * REGBYTES(sp)
- LOAD x23, 23 * REGBYTES(sp)
- LOAD x24, 24 * REGBYTES(sp)
- LOAD x25, 25 * REGBYTES(sp)
- LOAD x26, 26 * REGBYTES(sp)
- LOAD x27, 27 * REGBYTES(sp)
- LOAD x28, 28 * REGBYTES(sp)
- LOAD x29, 29 * REGBYTES(sp)
- LOAD x30, 30 * REGBYTES(sp)
- LOAD x31, 31 * REGBYTES(sp)
- addi sp, sp, 32 * REGBYTES
- mret
|
